Semiconductor memories are vital components of microelectronic systems such as computers and other micro-processor based applications ranging from satellites to consumer electronics. Therefore, advances in the fabrication of semiconductor memories, including process enhancement and technology developments through the scaling for higher densities and faster speeds, help establish higher performance standards for other digital logic families.
Semiconductor memories are generally characterized as either volatile or non-volatile. In volatile memories, information is stored either by setting the logic state of a bi-stable flip-flop such as in a static random access memory (SRAM), or through the charging of a capacitor as in a dynamic random access memory (DRAM). In the either case, data are stored and can be read out as long as the power is applied, but are lost when the power is turned off.
Non-volatile memories such as mask read only memory (MROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), and electrically erasable programmable read only memory (EEPROM) are capable of storing data, even with the power turned off. The non-volatile memory data storage mode may be permanent or reprogrammable, depending upon the fabrication technology used. Non-volatile memories are used for program and microcode storage in a wide variety of applications in the computer, avionics, telecommunications, and consumer electronics industries. A combination of single-chip volatile as well as non-volatile memory storage modes is also available in devices such as non-volatile SRAM (nvRAM) for use in systems that require fast, reprogrammable non-volatile memory. In addition, dozens of special memory architectures have evolved which contain some additional logic circuitry to optimize their performance for application-specific tasks.
Some types of non-volatile memory devices such as MROM, PROM, and EPROM are either incapable of being erased and re-written, or must be removed from the system to be erased and reprogrammed. EEPROM is electrically erasable and writable while installed in a system and has been widely used in applications requiring continuous reprogramming such as system programming or as subsidiary memory devices. One type of EEPROM know as flash EEPROM (“flash memory”) is advantageously used for mass storage in subsidiary devices because its high integration density as compared with conventional EEPROM. Two common types of flash memory are NAND-type (which generally has higher integration densities) and NOR-type.
A NAND-type flash memory device includes a memory cell array region for storing information. The memory cell array is formed by a plurality of cell strings called NAND strings. A page buffer circuit is used to store data into or read data from the memory cell array in a flash memory. Memory cells in NAND-type flash memory are erased and programmed using the well-known F-N (Fowler-Nordheim) tunneling current technique. Such erasing and programming methods are disclosed in U.S. Pat. No. 5,473,563 entitled “NONVOLATILE SEMICONDUCTOR MEMORY” and U.S. Pat. No. 5,696,717 entitled “NONVOLATILE INTEGRATED CIRCUIT MEMORY DEVICES HAVING ADJUSTABLE ERASE/PROGRAM THRESHOLD VOLTAGE VERIFICATION CAPABILITY”.
To store data in a memory cell array, a data loading command is first applied to a flash memory. Then, address and data are successively input to the flash memory. Data to be programmed are generally transmitted sequentially to a page buffer circuit in byte or word units. Once the page buffer circuit is full, all of the data in the page buffer circuit are simultaneously programmed into the memory cell array (in the memory cells corresponding to the selected page) in response to a program command. A cycle (also referred to as a “program cycle”) in which data is programmed consists of a plurality of program loops. Each of the program loops is divided into two portions, e.g., a program portion and a program verification portion. During the program portion, the memory cells are programmed under a given bias condition in a manner well known in the art. During the program verification portion, the memory cells are accessed to verify that they have been programmed to a predetermined threshold voltage. The above-mentioned program loops are carried out repeatedly until all memory cells are verified as programmed, up to a certain maximum amount of time. During a program verification operation, data is accessed in the same manner as a normal operation, except that the read data are only used to internally verify the programming operation.
Various verification methods have been suggested in order to determine whether or not memory cells are programmed to wanted threshold voltages. One typical example is a wired-OR scheme of the type disclosed in U.S. Pat. No. 5,299,162 entitled “NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND AN OPTIMIZING PROGRAMMING METHOD THEREOF” (“the '162 patent”) which is incorporated herein by reference. FIG. 1 is a block diagram showing a memory device disclosed in the '162 patent. The memory device includes a program-status detecting circuit PS, which receives data stored in latches LT of a page buffer during a program verification portion and detects whether or not input data values indicate a program data value. For example, when all selected memory cells are programmed in an optimized state, the program-status detecting circuit PS outputs a normal detecting signal. If at least one selected memory cell is insufficiently programmed, the program-status detecting circuit PS outputs an abnormal detecting signal.
In a wired-OR type program verification method, the states of the selected memory cells are simultaneously detected, so the program verification time is short. When there are physical defects (e.g., adjacent page buffers are electrically connected) in page buffers, however, the program verification operation is influenced by the defective page buffers. In other words, even though the page buffers are replaced, the output of the program-status detecting circuit PS always indicates a program fail. To overcome these problems, a column scan type program verification method (also referred to as a “Y-scan” type) has been introduced in recent years. An example of a memory device adopting a column scan type program verification method is disclosed in U.S. Pat. No. 6,282,121 entitled “FLASH MEMORY DEVICE WITH PROGRAM STATUS DETECTION CIRCUITRY AND THE METHOD THEREOF” (“the '121 patent”) which is incorporated herein by reference. FIG. 2 is a block diagram showing the memory device disclosed in the '121 patent.
The memory device of FIG. 2 includes a program-status detecting circuit 190. During a program verification operation, data bits read by a page buffer circuit 110 are transmitted through a column gate circuit 140 to the program-status detecting circuit 190 in a preset unit, e.g., a byte or word unit. The program-status detecting circuit 190 detects whether all input data bits have been programmed to the correct data value. Depending on the detection result, the program-status detecting circuit 190 increments an address counter 120. Accordingly, the read data bits in the page buffer circuit 110 are not detected at the same time, and they are transmitted through a column gate circuit 140 to the program-status detecting circuit 190 in preset units. That is, the read data in the page buffer circuit 110 are scanned in preset units to verify programming.
A program verification operation using the above-described Y-scan technique accesses data in the same manner as a normal read operation except that the read data is only used internally during a program verification operation. The program cycle consists of several program loops, each including program portion and a program verification portion. As such, the entire program time is limited by the amount of time required to perform program verification operation.